The present invention relates to a logic simulation system for a digital logic circuit and, more particularly, to a logic simulation system suitable for inspecting the logic operation of a large-scale logic circuit at high speed.
One of the serious problems affecting the development of a computer relates to the debugging of the logic (e.g., the logic inconsistency arising inside of the computer, when an instruction is to be executed, so that an ordinary execution result cannot be obtained).
Especially a large-sized computer in recent years has large-scaled and complicated circuitry so that it uses a number of LSIs. If a large number of logic inferiorities occur in the LSIs, troublesome work, is required for remaking those LSIs, which undesirably impacts upon the development term. This makes it far more necessary to extract the logic inferiorities at an early stage thereby to make logic simulation indispensable. In the current practice, more specifically, the results when a designed circuit is operated are computed from the design data of the circuit by the computer or the like, thereby to judge whether or not a logic inferiority has existed in the original circuit design.
The logic simulation per se is disclosed in the following book:
Title: PA0 Authors: PA0 Publisher:
Diagnosis & Reliable Design of Digital Systems (Chapter 4: Logic Level Simulation, pp. 174 to 248): PA1 Melvin A. Breuer PA1 Arthur D. Friedman: PA1 Computer Science Press, Inc. PA1 Digital System Design Series.
Many large-scale computers or VLSIs adopt a synchronous type logic circuit. In this synchronous logic circuit, flip-flops and combination circuits are so connected that the flip-flops are operated in synchronism with clocks by using the clocks without fail in the set and reset conditions of the flip-flops to apply the output of each flip-flop to another flip-flop through the combination circuits.
By making use of that feature of the synchronous type logic circuit, the following logic simulation method has been developed (as disclosed in Japanese Patent Application No. 28536/1984, filed on Feb. 20, 1984).
More specifically, a predetermined input signal value is given to a combination circuit surrounded between flip-flops (which are also called "latches"). Assuming that the delay time of the circuit elements (which are also called "gates") in the combination circuit having logic operation functions such as AND, OR or NOT is zero, output signal values are sequentially evaluated (i.e., the logic operation for computing the output signal values from the input signal values) from the input signal values of individual circuit elements at clock time (which is called a "time step"), based on an event drive system, to compute the output signal values from the aforementioned combination circuits. Here, the event drive system is a system for sequentially evaluating, while selecting at each time step, only such circuit elements included in the aforementioned combination circuits as may possibly have their input signal values changes between the preceding time step and the present time step, and accordingly have their output signal values varying. Incidentally, the "event" defined herein has a wide meaning of circuit elements themselves, in which the signal values have varied, and a narrow meaning of circuit elements themselves in which the input signal values have varied.
Of the output signal values outputted from the combination circuits, moreover, the output signal values of the flip-flops made receptive of the varying output signal values of the circuit elements are evaluated (or computed) from input values and clock phases to be fed to those flip-flops.
If the simulation based on the method described above is practised, many variations of the clock signal values occur. This is caused by the fact that the operations of the synchronous type logic circuits are conducted by the data transfer between the latches made receptive of the clock signals.
For example, a logic circuit as shown in FIG. 1 will be examined in the following. In FIG. 1: reference numerals 11, 12 and 13 denote input lines providing an external input signal IN, a clock signal CLK and a constant level signal CONST, respectively; character g.sub.1 denotes an OR gate; character g.sub.2 denotes an AND gate; and character l.sub.1 denotes a latch (which is also called a "flip-flop"). The lines 11 to 13 will be referred to hereinafter as the "IN terminal", the "CLK terminal" and the "CONST terminal", respectively. In case the time period (which is called a "machine cycle") for executing fundamental operations in a logic unit is divided into one or more processing time units (i.e., 0, 1, 2, - - -, and n-1), as shown in FIG. 2, clock signal specifies those processing time units.
Moreover, the, clock signals corresponding to the individual time units will be sequentially called the "clock signals having clock phase numbers 0 to n-1" and denoted by C.sub.0 to C.sub.n-1 for simplification. FIG. 2 shows the four clocks C.sub.0 to C.sub.3, for example.
In case the signal IN varies after the clock signal has varied in the sequence of "0"-"1"-"0", as shown in FIG. 2, the outputs of the gates g.sub.1 and g.sub.2 and the latch l.sub.1 will vary, as shown in FIG. 3. In a machine cycle MCO, more specifically, the output of the gate g.sub.1 varies in response to the rise and fall of the clock signal C.sub.0. In a machine cycle MC.sub.1, the outputs of the gates g.sub.1 and g.sub.2 and the latch l.sub.1 will vary in response to the rise of the clock signal C.sub.0, and the outputs of the gates g.sub.1 and g.sub.2 will fall in response to the fall of the clock signal C.sub.0.
In the case of the logic simulation of this circuit, the aforementioned Patent Application is required in accordance with the variations of the clock signal to have the evaluations (i.e., the logic operations for computing the output signal values from the input signal values) of the element g.sub.1 made receptive of the clock signal, the element g.sub.2 made receptive of the output of the element g.sub.1, and the output of the element l.sub.1 made receptive of the element g.sub.2. Incidentally, without variation of the clock signal value, no evaluation of each element becomes necessary, and the previous output signal value may be referred to as it is. As the scale of the circuit is enlarged, the computation time period for this evaluation is markedly extended.
These variations of the clock signal never fail to be experienced as two per machine cycle, i.e., the rise of `0`.fwdarw.`1` and fall-down of `1`.fwdarw.`0` of the clock signal so that a number of ineffective element evaluations will occur. Here, the "ineffective element evaluation" means a useless element evaluation exerting no influence upon the actual logic operations.
As shown in FIG. 3, for example, the rise and fall of the clock, as indicated at circled b and c, will not influence the latch l.sub.1. Incidentally, the evaluations encircled d to g of the element have been practised in the prior art.
Therefore, it could be expected to drastically improve the logic simulation processing speed if the useless element evaluations of the variations of the clock signals caused by the rise/fall of the clock signals could be suppressed as much as possible.